Materials and Methods for Fabricating Superconducting Quantum Integrated Circuits

ABSTRACT

Materials and methods are disclosed for fabricating superconducting integrated circuits for quantum computing at millikelvin temperatures, comprising both quantum circuits and classical control circuits, which may be located on the same integrated circuit or on different chips of a multi-chip module. The materials may include components that reduce defect densities and increase quantum coherence times. Multilayer fabrication techniques provide low-power and a path to large scale computing systems. An integrated circuit system for quantum computing is provided, comprising: a substrate; a kinetic inductance layer having a kinetic inductance of at least 5 pH/square; a plurality of stacked planarized superconducting layers and intervening insulating layers, formed into a plurality of Josephson junctions having a critical current of less than 100 μA/μm2; and a resistive layer that remains non-superconducting at a temperature below 1 K, configured to damp the plurality of Josephson junctions.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is Continuation of U.S. patent Ser. No. 17/307,931, filed May 4, 2021, now U.S. Pat. No. 11,508,896, issued Nov. 22, 2022, which is a Non-Provisional of, and claims benefit of priority from, U.S. Provisional Patent Application No. 63/034,367, filed Jun. 3, 2020, the entirety of which are expressly incorporated herein by reference in its entirety.

FIELD OF THE INVENTION

The present invention relates to the field of fabrication of superconducting integrated circuits, and more particularly to fabrication of superconducting integrated circuits for application to quantum computing.

BACKGROUND OF THE INVENTION

Each reference cited herein is expressly incorporated herein by reference in its entirety for all purposes.

Superconducting integrated circuits (ICs) based on Josephson junctions (JJs) are capable of operation with very low power and high speed, orders of magnitude beyond those possible using conventional semiconducting circuits. Techniques have been developed that permit fabrication of superconducting ICs with many thousands of JJs, including a plurality of superconducting wiring layers and vias connecting them. These have found application in circuits and systems for classical computing (i.e., performing primitive mathematical and logic operations), including those based on single-flux-quantum (SFQ) voltage pulses. These have generally been based on the superconductor niobium (Nb), and JJs based on Nb/AlOx/Nb tunnel junctions, with a barrier layer of aluminum oxide on the 1-nm scale.

See, for example, “Double-Masking Technique for Increasing Fabrication Yield in Superconducting Electronics” (U.S. Pat. Nos. 7,615,385; 8,383,426; 9,136,457; 9,595,656; 10,109,673); “System and Method for Providing Multi-Conductive Layer Metallic Interconnects for Superconducting Integrated Circuits” (U.S. Pat. Nos. 8,301,214; 8,437,818; 9,130,116; 9,741,920); and “Method for increasing the integration level of superconducting electronic circuits” (U.S. Pat. Nos. 9,741,918; 10,283,694).

Similar circuits may be integrated on the same chip as cryogenic magnetic memory cells (“System and methods for cryogenic hybrid technology computing and memory”; U.S. Pat. No. 10,460,796), superconducting photon detectors (“Integrated Superconducting Nanowire Digital Photon Detector” Ser. No. 16/016,149; “Superconducting optical-to-digital converter” Ser. No. 16/149,910), or ultra-low dissipation power distribution circuits (“Low-power biasing networks for superconducting integrated circuits”; U.S. Pat. No. 9,853,645).

Similar high-speed superconducting integrated circuits may be fabricated on a plurality of chips configured on a multi-chip module (MCM). See, for example, “Superconducting multi-chip module for high-speed digital circuits” (U.S. Pat. Nos. 8,937,255; 9,647,194); “Method of forming an electronic multichip module” (U.S. Pat. No. 8,804,358); “Method for electrically interconnecting at least two substrates and multi-chip module” (U.S. Pat. No. 10,373,928); “System and method for superconducting multichip module” (US 2020/011,925).

U.S. Pat. No. 10,403,808 provides a superconducting wafer stack, with insulators and dielectrics.

In recent years, new applications have been developing for superconducting integrated circuits in the field of quantum computing. These are also generally based on Josephson junctions, although materials and devices with reduced loss may be necessary to operate at extremely low (mK) temperatures. See, for example, “Systems and methods for fabrication of superconducting integrated circuits” (U.S. Pat. No. 9,978,809); “Method of forming superconducting apparatus including superconducting layers and traces” (U.S. Pat. No. 10,651,362); “Microwave integrated quantum circuits with vias and methods for making the same” (U.S. Pat. No. 9,971,970); “Chips including classical and quantum computing processors” (US 2017/0177534).

Conventional superconducting electronic design rules are optimized for operation at around 4 K. It is known that cooling capacities are small at low temperatures, tending to scale with T or even more strongly. For example, a semiconductor chip at room temperature may dissipate 1 W or more, while superconducting chips at 4 K can have power levels of a few mW. However, superconducting quantum circuits tend to operate at temperatures of order 10 mK (0.01 K), where power levels should be restricted to a few microwatts (μW).

Several techniques have been developed in the prior art to reduce power dissipation in superconducting circuits. In conventional RSFQ circuits, most of the power dissipation is associated with resistors in the power distribution network. In an alternative biasing scheme (known as EERSFQ or eSFQ), resistors are replaced by Josephson junctions and inductors, but large inductors may be difficult to integrate into the design scheme.

A further concern for quantum circuits is the need to maintain quantum coherence for relatively long times, which requires reducing defects and fluctuations in insulating layers near the active devices, as well as in the devices themselves. For example, amorphous materials such as silicon dioxide (SiO₂) may have atomic defects, and atomic hydrogen may diffuse into tunnel barriers of niobium Josephson junctions.

While some of these issues have been addressed in circuits with just a few superconducting quantum bits (qubits), practical quantum computers will require circuits with thousands of physical qubits. Furthermore, for efficient control and input/output, these quantum circuits should be interfaced with a similar number of classical superconducting circuits at the same temperature. This scaling has not yet been consistently demonstrated.

What is needed are methods of fabricating and packaging superconducting integrated circuits and systems, which retain the compatibility with design tools and scaling of classical superconducting circuits, while enhancing the performance of quantum and hybrid quantum/classical circuits at ultralow mK temperatures.

Quantum computing entails coherently processing quantum information stored in the qubits of a quantum computer. In certain types of quantum computing processors, such as quantum annealers or gate-based quantum processors, the qubits of the quantum processor are coupled together in a controllable manner such that the quantum state of each qubit affects the corresponding quantum states of the other qubits to which it is coupled.

In quantum computers that use qubits formed from superconductor materials, atomic-level defects characterized as two-level systems may reduce the quantum coherence of the qubits. Such two level systems are typically found on the surfaces and interfaces of the materials used to fabricate the qubits and other components of the computers. The fabrication of superconducting integrated circuits must be done in a way that minimizes the number of these defects located near the qubits.

To expand the number of qubits available for coupling in a solid state quantum processor, such as a quantum computer having superconducting quantum devices, one approach is to construct the quantum devices within the processor using 3D integration. That is, instead of fabricating the qubits and other quantum devices of the processor within a single plane that extends along one and/or two dimensions (e.g., x- and/or y-directions), the quantum devices can also be formed in one or more layers extending into a third dimension (e.g., z-direction). 3D integration also allows, in certain implementations, for greater connectivity and increases in quality factors associated with resonator devices. Moreover, 3D integration can, in some cases, provide a substantial reduction of crosstalk, since multiple layers of ground planes can be used to isolate drivelines and undesired coupling to other qubits, among other sources of cross-talk.

Embodiments of the quantum subject matter and quantum operations described in this specification can be implemented in suitable quantum circuitry or, more generally, quantum computational systems, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. The term “quantum computational systems” may include, but is not limited to, quantum computers, quantum information processing systems, quantum cryptography systems, or quantum simulators.

The terms quantum information and quantum data refer to information or data that is carried by, held or stored in quantum systems, where the smallest non-trivial system is a qubit, i.e., a system that defines the unit of quantum information. It is understood that the term “qubit” encompasses all quantum systems that may be suitably approximated as a two-level system in the corresponding context. Such quantum systems may include multi-level systems, e.g., with two or more levels. By way of example, such systems can include atoms, electrons, photons, ions or superconducting qubits. In many implementations the computational basis states are identified with the ground and first excited states, however it is understood that other setups where the computational states are identified with higher level excited states are possible. It is understood that quantum memories are devices that can store quantum data for a long time with high fidelity and efficiency, e.g., light-matter interfaces where light is used for transmission and matter for storing and preserving the quantum features of quantum data such as superposition or quantum coherence.

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SUMMARY OF THE INVENTION

In order to meet the requirements of designing superconducting quantum and classical circuits to operate at mK temperatures with reduced dissipation and increased coherence times, the following improvements over standard design rules for classical superconducting circuits at 4 K have been made.

1) Reduced-Loss Insulating Layers

In prior-art superconducting integrated circuit processes, there are multiple (e.g., 4) superconducting wiring layers with insulating layers between them. In a preferred embodiment, the insulating layers are changed from silicon dioxide (SiO₂) as used in the prior art to silicon nitride (SiN_(x)). The silicon nitride films (produced by plasma enhanced chemical vapor deposition) are believed to have fewer defects and permit longer coherence times than SiO₂. Furthermore, insulating layers near a qubit are removed to the extent possible, even layers on a classical control circuit that may be bump-bonded to the qubit. In a still further modification, even the native silicon dioxide on the silicon wafer substrate is removed before depositing the metals. This might in principle permit conduction through the substrate, except that the semiconducting substrate is virtually insulating and has virtually no carriers at the ultralow temperatures.

2) Josephson Junctions with Reduced Critical Current

The standard superconducting electronic process permits Nb/AlOx/Nb Josephson junctions on submicron scales. The standard minimum critical current in Josephson junctions for circuits optimized for operating at 4.2 K is about 100 μA, in order to avoid effects of thermal fluctuations. For circuits operating at 40 mK, the critical current can be reduced to as low as about 1 μA, which dramatically reduces power dissipation per junction. For this reason, in the revised integrated circuit fabrication process, the critical current density Jc of the Josephson junctions (determined by the thickness of the tunnel barrier) is reduced to 1 kA/cm² (10 μA/μm²), as compared with the previous standard process with Jc=20 kA/cm². For a junction with area˜0.1 μm², this yields Ic˜1 μA.

3) Kinetic Inductive Layer

Superconducting integrated circuits require lossless inductances, which are generally produced by superconducting transmission line structures. A typical circuit inductance may be as large as L˜Φ₀/Ic, where Φ₀=2 mA-pH (picoHenrys) is the magnetic flux quantum. For Ic˜1 μA, this requires L˜2000 pH, which is quite large on the μm scale. Inductances for low-power current distribution can be even larger. In order to properly design these large inductors, an additional superconducting wiring layer is added, based on ultrathin NbN films. These NbN films exhibit extra “kinetic inductance” not associated with a magnetic field, corresponding to a film thickness d much less than the relatively large superconducting penetration depth of NbN. For films ˜40 nm thick, the kinetic inductance is of order 10 pH/square. This enables the design of inductors that are considerably more compact than would otherwise be required for these low-Ic superconducting circuits. In a preferred process presented herein, the high-kinetic-inductance layer is placed below the Nb ground plane, as the first layer (MN1) on top of the silicon wafer.

4) Resistive Layer

Superconducting electronic circuits require a resistive layer, for use in damping Josephson junctions and in current distribution networks. While inductors may be substituted for resistors in biasing networks, shunt resistors for the junctions are still needed for classical single-flux-quantum (SFQ) circuits at ultralow temperatures. The standard resistive layer in prior classical superconducting circuits was the metal molybdenum (Mo), which however becomes superconducting (and therefore non-resistive) at temperatures below about 1 K. For this revised quantum-compatible process, the resistive layer comprises a 40 nm layer of PdAu, which remains non-superconducting down to the mK range. This may also incorporate very thin Ti adhesion layers (Ti/PdAu/Ti), but this remains resistive with a resistance of about 2 ohms/square.

5) Superconducting Bump Bonds

In a preferred embodiment, superconducting qubit chips may be mounted on top of a carrier (multi-chip module or MCM) comprising superconducting control circuits (or vice versa). It is preferred that the bump act as a zero-resistance electrical connection between the two circuits, which can transmit SFQ pulses from the control circuit to the quantum circuit, and also maintain a small fixed spacing between the two circuits. Following the prior art, one preferred embodiment of the bump bonds comprises the combination of micron-scale copper posts and indium adhesive bonds. Below a temperature of 3.4 K, the indium is superconducting, so that these bonds have the necessary superconducting properties for operation at mK temperatures.

6) Planarized Layers

To increase the reliability of a scalable multilayer process for fabricating superconducting integrated circuits, we have developed a custom wafer-scale planarization process, based on chemical-mechanical polishing, which is compatible with the new silicon nitride dielectric layers. This does not damage the superconducting layers or Josephson junctions. This is described further below.

7) Reducing Hydrogen Contamination Effects

It is well known that hydrogen ions (protons) diffuse easily through transition metals such as Nb. Furthermore, it is believed that hydrogen atoms may alter the properties of Nb Josephson junctions by their presence in or near the tunnel barrier, introducing variability and noise. One way to address this in the prior art (U.S. Pat. No. 8,301,214) is to insert hydrogen diffusion barrier layers at several key steps in the process. Similar diffusion barriers may be incorporated into the current improved process. A complementary approach is to deliberately introduce deuterium atoms (heavy hydrogen) at a key step in the process. The heavier deuterium atom has a reduced diffusion constant, but also has a different nuclear spin that may exhibit reduced noise properties, potentially contributing to enhanced quantum coherence times. It is suggested that deuterium may be incorporated into the process by the use of deuterated carrier gases such as silane and hexamethyldisilazane (HMDS).

These are a few of the many improved materials and methods that may be used to improve the performance, reproducibility, and scaling of superconducting circuits for quantum computing. A preferred embodiment of the invention may include any or a combination or subcombination of these, or others that follow the same general approach of reducing power, enhancing quantum coherence, and promoting scaling for superconducting circuits at ultralow temperatures.

It is therefore an object to provide an integrated circuit system for quantum computing, comprising: a substrate; a kinetic inductance layer having a kinetic inductance of at least 5 pH/square; a plurality of planarized superconducting layers and intervening insulating layers, the insulating layers, formed into a plurality of Josephson junctions having a critical current density of less than 100 μA/μm²; and a resistive layer that remains non-superconducting at a temperature below 1 K, configured to damp the plurality of Josephson junctions. The substrate may be silicon. The insulating layers may be a nitride, e.g., silicon nitride.

It is also an object to provide a method of forming an integrated circuit system for quantum computing, comprising: providing a substrate; forming a kinetic inductance layer having a kinetic inductance of at least 5 pH/square; depositing a plurality of superconducting layers and intervening insulating layers, the insulating layers comprising silicon nitride; patterning the plurality of superconducting layers and intervening insulating layers into Josephson junctions having a critical current density of less than 100 μA/μm²; planarizing the plurality of superconducting layers and intervening insulating layers; and forming a resistive layer that remains non-superconducting at a temperature below 1 K, to damp the Josephson junctions.

It is a further object to provide a superconducting integrated circuit adapted to operate at a temperature below 0.5 K, comprising: a kinetic inductance layer having a kinetic inductance of at least 5 pH/square, patterned into at least one inductor; a planarized plurality of superconducting layers and intervening insulating layers configured to galvanically isolate the superconducting layers, formed into a plurality of submicron Josephson junctions having a critical current density of less than 100 μA/μm²; and a resistive layer that remains non-superconducting at a temperature of 0.5 K, configured into a resistive shunt for damping a Josephson junction.

Another object provides a method of forming an integrated circuit on a substrate, adapted to operate at a temperature below 0.5 K, comprising: forming and patterning a kinetic inductance layer having a kinetic inductance of at least 5 pH/square; depositing a plurality of superconducting layers and intervening insulating layers, at least one insulating layer being planarized; patterning the plurality of superconducting layers and intervening insulating layers into Josephson junctions having a critical current density of less than 100 μA/μm²; and forming a resistive layer that remains non-superconducting at a temperature of 0.5 K, to damp the Josephson junctions.

The integrated circuit system may comprise a plurality of interconnected substrates, wherein the respective substrates are aligned with each other to provide selective galvanic contact. The substrates are bonded, for example by indium copper bumps, or cryogenic adhesive, such as suitable epoxies. The substrate functionality may be partitioned, such that some substrates comprise Josephson junction-based classical computing devices and other comprise qubits, or the functions may be disperse across the same substrates. A plurality of superconducting qubits on one substrate may therefore be coupled to a classical superconducting circuit comprising at least one of the plurality of Josephson junctions on another substrate.

The opposed substrates may have protruding posts and corresponding trenches to assure precision alignment therebetween. Enhanced planarity may be achieved by use of copper pedestals which mate with a planarized surface of the mating chip.

The superconducting integrated circuit may be adapted to operate, and be operated, at a temperature below 100 mK, 50 mK or 10 mK, and the resistive layer remains non-superconducting at a corresponding temperature of 100 mK, 50 mK, or 10 mK. The resistive layer may comprise a 40 nm layer of PdAu.

The superconducting integrated circuit may be formed on a silicon substrate. The silicon substrate may have an oxide-free interface to a superconducting layer, and is preferably cleared of the oxide layer before deposition of a metal layer on it, e.g., the oxide layer is removed.

At least one insulating layer may comprise silicon nitride. Each insulating layer may comprise silicon nitride. Each insulating layer may consist essentially of silicon nitride. The intervening insulating layers may be configured to galvanically isolate the superconducting layers.

The kinetic inductance layer may have a kinetic inductance of at least 8 pH/square, e.g., about 10 pH/square.

The kinetic inductance layer may be patterned as an inductor. The kinetic inductance layer may comprise a meander inductor. The kinetic inductance layer may be patterned into a current distribution network.

The plurality of Josephson junctions may have a critical current density of less than 50 μA/μm², e.g., about 10 μA/μm².

A bump bond comprising indium may be provided for joining the substrate to another circuit. The bump bond may comprise a micron-scale copper post and indium adhesive bond.

The integrated circuit may comprise deuterium diffused into the Josephson junction. The plurality of planarized superconducting layers and intervening insulating layers, or the superconducting integrated circuit, may comprise at least one hydrogen diffusion stop layer. The integrated circuit system may further comprise at least one hydrogen diffusion stop layer. The integrated circuit system may further comprise deuterium diffused into a transition metal layer. The method may further comprise diffusing deuterium into the Josephson junction and/or a transition metal layer, and/or fabricating the integrated circuit with a deuterated reagent. At least one hydrogen diffusion stop layer may be formed.

It is also an object to provide an integrated circuit system for quantum computing, comprising: a substrate which is non-superconducting at a temperature below 1 K; a kinetic inductance layer, formed over the substrate, having a kinetic inductance of at least 5 pH/square; a plurality of stacked planarized superconducting layers and intervening insulating layers, formed over the kinetic inductance layer, and patterned into a plurality of Josephson junctions having a critical current of less than 100 μA/μm²; and a patterned resistive layer, that remains non-superconducting at a temperature below 1 K, formed over the plurality of stacked planarized superconducting layers and intervening insulating layers, and being configured to form Josephson junction damping elements for damping the plurality of Josephson junctions.

The superconducting integrated circuit may be configured as a control chip for generating single flux quantum pulses, for controlling a superconducting qubit on a different chip, both the superconducting integrated circuit and the superconducting qubit on a different chip operating at the same temperature. The superconducting integrated circuit may generate single flux quantum (SFQ) pulses. The SFQ pulses may control a superconducting qubit integrated circuit. The integrated circuit and the superconducting qubit integrated circuit may be on different chips, with both the superconducting integrated circuit and the superconducting qubit integrated circuit operating at the same temperature.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a cross-sectional view of a High Kinetic Inductance Layer.

FIG. 2 shows a cross-sectional view of a Josephson Junction layer.

FIG. 3 shows a cross-sectional view of a top ground layer.

FIG. 4A shows a cross-sectional view of a control chip near a qubit chip.

FIG. 4B shows a cross-sectional view of a control chip near the qubit chip, with lowered participation ratio than that shown in FIG. 4A.

FIG. 5 shows a cross-sectional view of a control chip bonded to a qubit chip.

FIG. 6A shows a top view of an exemplary circuit of section of a control chip.

FIG. 6B shows a cross section across line 6B-6B of a portion of the control chip.

FIG. 7A shows a quantum chip and control chip aligned using mating post and trench technology.

FIG. 7B shows a quantum chip and control chip with copper pedestals aligned using mating post and trench technology.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows a cross-sectional view of the lowest layers of wiring on the silicon substrate. The vertical dimensions are not necessarily to scale, and the horizontal dimensions here are arbitrary.

The silicon substrate is a high-resistance silicon wafer (typically 15 cm in diameter), with the native oxide removed. Note the presence of a patterned High-Kinetic Inductance (HKI) layer directly on the substrate, comprising a NbNx superconducting film with a kinetic inductance here of 8.5 pH/square. This is also called the MN1 layer, for metal nitride. This might be used as an inductor in a memory loop or a bias line, for example. The M0 layer is the superconducting ground plane, which could be Nb or NbN.

The IN1 layer is the low-loss silicon nitride insulator layer that separates MN1 from M0, unless a via is needed to connect the two wiring layers. Silicon nitride is also used for the I0 layer above M0. The I0 layer is planarized (using a form of chemical-mechanical polishing or CMP) to form a flat substrate for a subsequent Josephson junction layer.

FIG. 2 shows a cross-sectional view of the middle layers of the superconducting IC, focusing on the Josephson junction. This is labeled J1, and lies between Nb wiring layers M1 and M2, with the junction area defined with an anodization ring A1 around the junction. The junction layer itself comprises a trilayer with Nb base and counter-electrode, and a very thin layer of A1 which is mostly oxidized to form the tunnel barrier between the two Nb layers. The critical current density of the junction is designed to be Jc=1 kA/cm² (10 μA/μm²) in the relevant mK regime. The R2 layer is the resistor layer, here comprising a Pd—Au alloy film with a resistance 4 ohms/square down to the mK range. Note that here the R2 layer provides a resistive shunt for the Josephson junction, which critically damps the junction so that it may generate a picosecond SFQ voltage pulse. Layers M1 and M2 are 135 and 300 nm thick, respectively.

FIG. 3 shows the cross section of the top layers of the superconducting circuit, including a 500 nm thick M3 layer of Nb, with a 100 nm top capping layer of Ta or NbNx. I2 is the silicon nitride insulating layer separating M2 from M3. The M3 layer may be a tantalum layer, or a niobium layer capped with tantalum, which forms a thinner native oxide layer than niobium.

FIG. 4A shows the cross-section of the patterned control chip, with a section etched away where it would be close to a qubit chip. FIG. 4B shows a cross-section of the patterned control chip, with a section etched away where it would be close to a qubit chip, having a lowered participation ratio. The flip-chip assembly is shown in FIG. 5 , where the qubit control loop is shown on top. FIG. 4A is a detail of FIG. 5 , as indicated. It may be inductively coupled to SFQ pulses from the control chip below. Note the spacing between the two chips provided by the 5 μm Cu posts and Indium pressed bumps, where the indium provides a superconducting link between the two chips at the mK operating temperature.

FIG. 6A shows a top view and FIG. 6B shows a corresponding cross-section for a section of a superconducting circuit of a control chip along section 6B-6B, showing multiple Josephson junctions, shunt resistors, inductors, and bias lines.

FIG. 7A shows a first embodiment of how precision alignment may be assured between the control chip 4 (digital logic) and the quantum chip 3 (qubits). Known anisotropic silicon wafer etching techniques using chlorine-based etches may be used to create silicon posts 1 on the quantum chip and matching silicon trenches 2 on the control chip. The interlocking pairs can be strategically placed around the two chips to minimize the tilt between the two chips. The resulting micron-scale alignment can be used both for galvanic electrical contact (via the Cu/In bumps 5) and non-contact capacitive and inductive coupling between the classical control chip and the quantum chip.

FIG. 7B shows a second embodiment which employs a copper pedestal for improved planarity with respect to the embodiment of FIG. 7A. While the control chip 4 (digital logic) and the quantum chip 3 (qubits) are not self-aligned, the copper pedestals can be planarized to ensure that the surfaces are parallel.

The indium on the bumps is superconductive at the operating temperatures of the device, below 3.4 K, and make contact with a superconducting surface of the adjacent chip. In some cases, the adjacent chip surface is subject to oxidation or otherwise needs protection, and advantageously, a thin gold film may be formed on top of a superconducting surface, which itself will be induced into superconductivity under operating conditions.

A) Exemplary Design Rules for Superconducting Quantum Control Circuit Electronics Fabrication: Process #QC1000A

1.0 General Description

1.1 This integrated circuit fabrication process uses only refractory materials, with the exception of a Pd/Au metallization layer used for contact pads. Niobium is used as the superconducting material due to its comparably high critical temperature, electrical and thermal stability, and ability to be thermally cycled many times without degradation. Niobium/Aluminum-Oxide/Niobium Josephson tunnel junctions are made by depositing an in-situ trilayer across the entire wafer and subsequently defining junction areas by deep-UV photolithography and etching. This method yields good uniformity and reproducibility of junction parameters.

1.2 The critical current density of Nb/AlOX/Nb trilayer associated with QC1000A is 1 kA/cm² (10 μA/μm²).

1.3 The Josephson junctions can be interconnected into circuit configurations using four superconducting layers: junction base electrode (layer M1), two Nb wiring layers (layers M2 and M3), superconducting NbNx ground plane (layer M0) and a NbNx high kinetic inductance layer below the ground plane (MN1)

1.4 The sheet resistance of the resistive layer (R2) is a Ti/PdAu/Ti resistive material with sheet resistance of 2.0 ohms/sq and a thickness of 100±10 nm.

1.5 Low loss SiNx is deposited to provide insulation between the conducting layers. Anodization of the base electrode of trilayer provides additional insulation to Josephson junctions.

1.6 QC1000A is fabricated on a 150-mm diameter (6-inch) high resistivity Si wafer.

1.7 QC1000A Process Flow Overview is shown in the table below.

Mask # Layer GDS# polarity Description Al/NbNx deposition 1 MN1 34 + MN1 layer patterning Low loss SiN_(x) deposition 2 IN1 32 − Contact (via) between MN1 and M0 patterning NbNx deposition 3 M0 30 − M0 patterning (holes in niobium ground plane) Low loss SiN_(x) deposition CMP “Caldera” planarization 4 I0 31 − Contact (via) between M1 and ground plane patterning Nb/Al/AlO_(x)/Nb trilayer deposition (see 1.2) 5 J1 4 + Counter-electrode (junction area) definition Base electrode anodization 6 A1 5 + Anodization layer patterning 7 M1 1 + Trilayer base electrode patterning Low loss SiN_(x) deposition 8 R2 9 + Resistive layer patterning Resistive layer deposition (see 1.4) Low loss SiN_(x) deposition 9 I1 3 − Contact (via) between M2 and (J1/J2, R2, or M1) Nb deposition 10 M2 6 + M2 layer patterning Low loss SiN_(x) deposition 11 I2 8 − Contact (via) between M2 and M3 Nb deposition 12 M3 10 + M3 layer patterning 13 I3 13 − I3 (Dielectric removal from Qubit interface) patterning 14 R3 11 + Contact pad patterning Pd/Au contact metallization deposition 15 BMP-Cu 12 + “bump” layer for MCM, Copper 16 BMP-In 15 + “bump” layer for MCM, Indium

Layout Design Rules

2.1 Minimal size, spacing, and surround for each layer are specified in the following table:

# Layer Rule μm Comment 1 MN1 Positive MN1 wiring layer 1.1 MN1 minimal size 0.8 1.2 MN1 minimal spacing 1.0 1.3 MN1 surround IN1 0.3 2 IN1 Negative Contact (via) between MN1 and M0 2.1 IN1 minimal size 0.8 2.2 IN1 surrounded by 0.3 MN1 2.3 IN1 spacing to M0 0.3 A via should always be covered with metal. M0 is a negative layer, −spacing” instead of “surrounded by” 2.4 IN1 edge spacing to J1 0.5 Crossing IN1 pattern with JJs is possible but not recommended 3 M0 Negative Holes in ground plane 3.1 M0 minimal size 0.5 3.2 M0 minimal spacing 0.5 3.3 M0 spacing to I0 0.3 A hole in insulation should always be over metal. M0 is a negative layer, −so, the rule is “spacing to”. 4 I0 Negative Contact (via) between M1 and ground plane 4.1 I0 minimal size 1.0 4.2 I0 spacing to J1 1.0 J1 patterns should not overlap with I0 patterns. 4.3 I0 surrounded by M1 0.3 A hole in insulation layer must be completely covered by two adjacent metal layers (from top and bottom) 4.4 I0 edge spacing to R2 0.3 5 J1 Positive Trilayer counter electrode (junction area) definition 5.1 J1 minimal size 0.6 5.2 J1 minimal spacing 1.0 5.3 J1 surrounded by A1 0.5 A JJ must be covered by anodization layer 5.4 J1 surrounded by M1 1.0 5.5 M0 edge spacing to J1 0.5 5.6 I0 edge spacing to J1 1.0 J1 patterns should not overlap with I0 patterns. 5.7 IN1 edge spacing to J1 0.5 Crossing J1 patterns with IN1 is not recommended. 6 A1 Positive M1 anodization layer patterning 6.1 A1 minimal size 1.0 6.2 A1 surrounded by M1 0.3 6.3 A1 edge spacing to R2 0.3 6.4 A1 edge spacing to I1 0.5 If hole in I1 is surrounded by A1, no galvanic contact to M1 is possible (except for via JJ) 7 M1 Positive Trilayer base electrode patterning 7.1 M1 minimal size 0.8 7.2 M1 minimal spacing 1.0 7.3 M1 edge spacing to R2 0.3 7.4 M1 surround I1 (7) 0.5 8 R2 Positive Resistive layer patterning 8.1 R2 minimal size 0.8 8.2 R2 minimal spacing 1.0 8.3 R2 surround I1 0.5 A simultaneous contact to both R2 and M1 layers is possible. The overlap area of I1 hole with each layer (R2 and M1) should satisfy rule 8.1 8.4 M0, M1, I0, or A1 0.3 R2 pattern may not cover steps in I0, A1 or M1. edge spacing to R2 Placing R2 object inside M0, I0, A1 or M1 area is allowed. 9 I1 Negative Contact (via) between M2 and (J1/J2, R2, or M1) 9.1 I1 minimal size 1.0 9.2 I1 surrounded by M2 0.5 10 M2 Positive M2 wiring layer 10.1 M2 minimal size 0.8 10.2 M2 minimal spacing 1.0 10.3 M2 surround I2 0.5 11 I2 Negative Contact (via) between M2 and M3 11.1 I2 minimal size 1.8 11.2 12 surrounded by M3 0.5 12 M3 Positive M3 wiring layer 12.1 M3 minimal size 2.0 12.2 M3 minimal spacing 2.0 12.3 M3 minimal contact 5.0 R3 layer is deposited directly on M3 (without with R3 insulation). To provide a reliable electrical contact between objects in R3 and M3 layers, the overlap should be no less than 5 microns. 13 I3 Negative Di-electric removal from selected area 13.1 I3 minimal size 1.8 13.2 I2 surrounded by M3 0.5 14 R3 Negative Pd/Au contact metallization 14.1 R3 minimal size 5.0 14.2 R3 minimal spacing 3.0 14.3 R3 surrounded by M3 0.5 15 BMP1 Negative Copper bumps layer for MCM 15.1 BMP minimal size 10 15.2 BMP minimal spacing 30 16 BMP2 Negative Indium bumps layer for MCM 16.1 BMP minimal size 15 16.2 BMP minimal spacing 30 16.3 BUM2 surround BNP1 2.5

3.0 Physical Layer Process Specifications

3.1 Since the fabrication process involves projection photolithography and etching, the size of features (e.g., linewidth) on the wafer may systematically differ somewhat from the designed feature size. This change in size is called “bias”. In the table below, the bias is defined as the shift of the object's edge due to its enlargement/reduction relative to its intended position in the design. It is often called single-side bias. A positive bias means that the digitized areas become larger on the wafer than in the design. The biases shown below for all layers, except J1/J2, are applicable to relatively extended objects with sizes larger that the minimal feature size for a given layer. In most cases, sharp corners will be rounded up.

Bias (3.1) Physical layer properties: Thickness Layer Material μm resistance, capacitance, etc. nm MN1 NbN_(x) 0.0 ± 0.1 Nb, superconductor. Penetration 40 ± 4 depth λ_(L) = 250 nm ± 5% IN1 SiN_(x) 0.0 ± 0.1 SiN_(x), insulator. Capacitance: 75 ± 7 0.24 fF/μm² ± 20% M0 NbN_(x) 0.0 ± 0.1 Nb, superconductor. Penetration 200 ± 10 depth λ_(L) = 250 nm ± 5% I0 SiN_(x) 0.0 ± 0.1 SiN_(x), insulator. Capacitance: 150 ± 15 0.31 fF/μm² ± 10% M1 Nb 0.0 ± 0.1 Trilayer base electrode, superconductor. 135 ± 10 λ_(L) = 100 nm ± 5% J1 Nb  0.0 ± 0.02 Josephson tunnel junction counter 50 ± 5 electrode (see 3.2 and 3.3) A1 Nb₂O₅/Al₂O₃ 0.0 ± 0.1 Layer of the anodized surface of base 40 ± 5 electrode (i.e., surrounding a Josephson junction). Capacitance: 5.0 fF/ μm² ± 20% SIN_(x) SiN_(x), insulator. Capacitance: 100 ± 10 0.52 fF/μm² ± 10% R2 Ti/PdAu/Ti 0.0 ± 0.1 2.0 ± 0.2 Ohm per square 40 ± 6 SiN_(x) SiN_(x), insulator. Capacitance: 100 ± 10 0.52 fF/μm² ± 10% I1 0.0 ± 0.1 Contact hole through the above two SiO₂ layers M2 Nb −0.1 ± 0.05 Nb, superconductor. Penetration 300 ± 20 depth λ_(L) = 80 nm ± 5% SIN_(x) SiN_(x) insulator. Capacitance: 500 ± 40 0.08 fF/μm² ± 10% I2 0.0 ± 0.1 Contact hole through the above insulator M3 Nb Capped with −0.3 ± 0.1  Nb, superconductor. Penetration 500 ± 50 Ta/NbNx depth: λ_(L) = 80 nm ± 5% 100 ± 10 I3 di-electric removal R3 Pd/Au 0.0 ± 1.0 Contact pads metallization 350 ± 60 BMP-Cu Cu/Au 0.0 ± 1.0 Copper Layer for MCM bump 6000 ± 600 BMP-In NbNx/In 0.0 ± 1.0 Indium Layer for MCM bump 3000 ± 300

3.2 Josephson junctions of circular shape are recommended. The deviation of the radius of the circle in J1 layer is within t 20 nm. If such a deviation is critical, use “digitized circular shape”, i.e., a polygon with vertices of 135 degrees placed on 20-nm grid.

3.3 The C₅ is the specific capacitance in fF/μm² and j_(c) is the critical current density in μA/μm², and plasma voltage in mV.

J_(c) (μA/μm²) 0.3 1.0 10.0 45.0 100.0 200.0 Cs (fF/μm²) 37 40 50 59 65 71 Vp (μV) 52 91 257 501 711 962

3.4 The critical current per micron width for superconducting films is given in the following table

Nb Layer MN1 M0 M1 M2 M3 I_(c) (mA/μm) 2.5 20.0 30.0 50.0 70.0

If the wire crosses over steps, its 1, may drop by more than 50%. The minimal width of a wire is shown in table 2.1 and its bias in table 3.0 before designing current transmitting lines.

3.5 The specific inductance of the superconducting films is given in the following table

Layer MN1-M0 M0-M1-M3 M0-M2-M3 M0-M2 Ls (pH/sq) 8.50 0.40 0.38 0.63

4.0 Lithography Features

4.1 Mask Grid Size Layer Polarity Grid Size [μm] MN1 Clear field 0.1 IN1 Dark field 0.1 M0 Dark field 0.1 I0 Dark field 0.1 M1 Clear field 0.1 J1 Clear field 0.02 J2 Clear field 0.02 A1 Clear field 0.1 R2 Clear field 0.1 I1 Dark field 0.1 M2 Clear field 0.1 I2 Dark field 0.1 M3 Clear field 0.1 I3 Dark field 0.1 R3 Dark field 0.1 BMP-Cu Dark field 0.1 BMP-In Dark field 0.1

4.2 Layer J1 have grid size of 20 nm. All remaining layers must use grid size of 100 nm. Every pixel coordinate is rounded up to a multiple of grid.

4.3 All layouts will be printed on wafers as you see them on your computer screen (no mirroring).

5.0 Designs Submission Formats

The format of layout file is GDS-II. The active chip area for the design is limited to 5,000 μm×5,000 μm. On the wafer, it will be surrounded by a dicing channel. Dicing channels between chips are 150 μm wide. No objects are allowed inside a dicing channel (extending beyond the 5,000 μm×5,000 μm area). In the case of 1-cm chips, the design area is 10,150 μm×10,150 μm. No objects are allowed beyond the 10,150 μm×10,150 μm area.

B. Substitution of Deuterium for Hydrogen to Reduce Noise in Quantum Circuits

This provides a method of manufacturing quantum devices where deuterium is incorporated into the devices either as an additional component or as a replacement of light hydrogen within the molecules of the component materials of the integrated circuits in order to reduce quasiparticles and intrinsic losses.

A basic challenge towards the creation of qubits is developing devices whose quantum coherence lasts long enough to enable control and measurement with error rates below the bounds requisite for quantum error correction.

For example, lossy materials within the mode volume of superconducting resonant structures impose a limit on how long such systems can store energy. Reducing the participation ratio of energy-storing non-vacuum materials (inclusive of surfaces, interfaces, thin films, and bulk matter) within the mode volume increases this limit. In particular, two-level systems present at surfaces and interfaces of superconducting qubits are believed to be a significant source of decoherence. The substrate to metal interface and substrate to air interface are believed to be a source of loss.

Deuterium is an isotope of hydrogen with a nuclear spin=1, unlike hydrogen which has a spin=1/2. The manipulation of nuclear spin by radiofrequency waves is important in chemical spectroscopy and medical imaging. When placed in a magnetic field, active nuclei absorb electromagnetic radiation at a frequency characteristic to the isotope. The resonant frequency, energy of the radiation absorbed, and the intensity of the signal are proportional to the strength of the magnetic field. Such a signal, although beneficial for chemical spectroscopy and medical imaging is a potential source of quasiparticles and losses in quantum devices.

Deuterium is most commonly used in hydrogen nuclear magnetic resonance spectroscopy (proton-NMR). NMR ordinarily requires compounds of interest to be analyzed as dissolved in solution. Because of deuterium's nuclear spin properties which differ from the light hydrogen usually present in organic molecules, NMR spectra of hydrogen/protium are highly differentiable from that of deuterium, and in practice deuterium is not seen by an NMR instrument tuned for light hydrogen. Deuterated solvents (including heavy water, but also compounds like deuterated chloroform, CDCl₃) are therefore routinely used in NMR spectroscopy, in order to allow only the light hydrogen spectra of the compound of interest to be measured, without solvent signal interference.

Exemplary embodiments include a qubit system, including a substrate layer, where the substrate surface is treated with a deuterated hexamethyldisilane (HMDS) immediately prior to metal deposition to reduce losses associated with the metal-substrate interface.

Additional exemplary embodiments include a method of fabricating a qubit system, where a crystalline silicon layer is grown epitaxially on the substrate using a deuterated silane source gas. The deuterated silane may also consist of an isotopically pure silicon-28 isotope for the formation of spin silicon qubits.

Further exemplary embodiments include a method of fabricating a qubit system, where superconducting quantum circuits containing Josephson junctions are employed for qubits on a quantum device which is bonded as a multi-chip module (MCM) to a classical superconducting electronic control circuit. The classical superconducting electronic control circuit consists of deuterated dielectric materials as insulators (i.e., deuterated tetraethyl orthosilicate glass (TEOS), silicon nitride with a deuterium impurity) that may be formed by employing plasma enhanced chemical vapor deposition (PECVD) with deuterated source gases (i.e., deuterated silane, deuterated ammonia).

C. Chemical-Mechanical Polishing (CMP) for Very Large Scale Integration of Classical and Quantum Superconducting Electronic Integrated Circuits

Conventionally, in the superconducting electronics field, a wiring pattern comprising a dense array of superconductive lines is formed by depositing a metal layer and etching to form a superconductive pattern. An insulating layer, typically formed of a dielectric material, is then applied to the wiring pattern and planarization of the dielectric material is achieved by chemical mechanical planarization.

Typically, the chemical mechanical planarization process for superconducting integrated circuits involves either planarizing the dielectric above or below the metal pattern without exposing the metal pattern, allowing for more wiring layers, but fails to provide stacked vias and high density VLSI chips. Another process, called the caldera process, also provides a planarized and exposed metal pattern. In the caldera process, the dielectric material is etched, exposing the metal pattern, then a silica-based slurry is utilized wherein the remaining dielectric material is planarized. The limitations of the caldera process are that it requires many processing steps, and has not yet been proven to provide stacked vias and other components on all microdevice layers. Currently, it is extremely difficult to planarize layers with both small and large structures while providing a highly uniform wafer surface, let alone in a reproducible manner while exposing a superconducting pattern.

According to a preferred embodiment, the surface of the integrated circuit is planarized in a pattern-independent manner comprising chemical-mechanical polishing, to selectively remove materials so as to leave an exposed Damascene pattern. Preferably, excess insulating material (e.g., silicon nitride) is removed from the metallic wiring. The conventional Damascene process is limited when the metal is removed at a low selectivity to the insulating material. When the metal removal rate is not selective enough to the insulating material, then the process severely erodes the insulator. The present approach addresses such a limitation, by enabling the use of a reverse Damascene process.

The reverse Damascene process also provides a planar surface with a wiring pattern embedded in an insulating layer. The embedded wiring pattern is formed by first etching a deposited metal or other conductive and/or superconductive material. Once the pattern is formed, a conformal insulating layer is deposited onto the patterned surface. The conformal insulating layer is chemically-mechanically polished to remove all insulator above the patterned layer. After polishing, the top surface of the patterned metallic, conductive and/or superconductive material is exposed but remains embedded in the insulating layer.

Currently, chemical-mechanical polishing (CMP) using a ceria-based slurry is adopted to achieve the formation of shallow trench isolation (STI) for element isolation in the manufacturing of semiconductor devices. STI is formed by providing a groove to a semiconductor substrate comprising a CMP stopper film, forming a silicon oxide film thereon, and removing the excess silicon oxide film by CMP. The stopper film is then removed in a subsequent processing step. Typically, the stopper film is a nitride such as silicon nitride.

According to the present technology, a novel application of silicon nitride and ceria-based slurries has been achieved, wherein the silicon nitride is the main dielectric used for insulation without the need for silicon oxide, and a stopper film is not required when either silicon oxide or silicon nitride dielectric insulation is used.

Alternatively, instead of ceria, other abrasives can be utilized such as silica or alumina. If the patterned metallic, conductive and/or superconductive material is a niobium-based material, then it is possible for a corrosive slurry to stop on the niobium-based material regardless of abrasive type.

Additives such as polymers, surfactants, inhibitors, and/or oxidizers may be added into the slurry for known purposes.

The superconductive material, dielectric material, slurry pH and abrasive type are not limited to the preferred embodiments.

The chemical-mechanical polishing may be performed in two or more steps rather than in one step provided in the preferred embodiment.

The polishing pad can be any of those which are conventionally employed in CMP, such as those comprising a cellular polyurethane pad. The polishing pad utilized in the preferred embodiment consists of a hard pad over a soft base pad. The hard pad consists of a cellular material while the soft base pad consists of a felt material.

The polishing parameters (i.e., slurry flow rate, down-force, table rotation) are optimized for maximum uniformity. The polishing parameters may also be set slightly above or below that of the preferred embodiment. The conditioning of the pad during CMP (i.e., in-situ or ex-situ) is preferred but not required.

The polishing process may be timed and calculated based on the rate of removal of the insulating material. The polishing process does not require the detection of an endpoint, through the use of metrology (i.e., ellipsometry, profilometry) or by any other means. Endpoint detection may also be employed. In addition, stopping the chemical-mechanical polishing process before the endpoint is reached and then reaching the endpoint in a second processing step (i.e., reactive ion etching, wet etching) is another embodiment.

Depositing a liner material (i.e., silicon nitride, tantalum nitride) as a stopping material over the metal, conductor and/or superconductor, to be later removed in a subsequent step is yet another embodiment.

These examples are not to be understood as limiting the invention, but rather as examples that illustrate the wide range of systems and applications that may become clear to those skilled in the art. The scope of the present invention includes the various combinations, subcombinations and permutations of the elements disclosed herein either expressly or through incorporation. No element shall be deemed critical or required unless specified as being a universally necessary element.

Each reference cited herein is expressly incorporated herein in its entirety, for its respective descriptions and teachings. 

What is claimed is:
 1. A superconducting integrated circuit configured to operate at a cryogenic temperature, comprising: a plurality of Josephson junctions formed from a plurality of superconducting layers, configured to switch at the cryogenic temperature; the at least one intervening insulating layer configured to galvanically isolate the plurality of superconducting layers at the cryogenic temperature; and a kinetic inductance layer patterned into a current distribution network for the plurality of Josephson junctions, the kinetic inductance layer having a higher unit inductance than the respective plurality of superconductive layers at the cryogenic temperature.
 2. The superconducting integrated circuit according to claim 1, further comprising a resistive layer, configured as a set of resistive elements to damp respective Josephson junctions which switch at the cryogenic temperature.
 3. The superconducting integrated circuit according to claim 1, further comprising a resistive layer which remains non-superconducting at a temperature below 0.5° K, configured as a set of resistive elements to damp respective Josephson junctions.
 4. The superconducting integrated circuit according to claim 1, wherein the kinetic inductance layer has kinetic inductance of at least 5 pH/square.
 5. The superconducting integrated circuit according to claim 1, wherein the cryogenic temperature is less than 0.5° K.
 6. The superconducting integrated circuit according to claim 1, wherein the plurality of Josephson junctions are planarized.
 7. The superconducting integrated circuit according to claim 1, wherein the kinetic inductance layer is configured as a ground plane on a substrate beneath the plurality of superconducting layers.
 8. The superconducting integrated circuit according to claim 1, wherein the plurality of Josephson junctions having a critical current density of less than 100 μA/μm².
 9. The superconducting integrated circuit according to claim 1, adapted to operate at a cryogenic temperature below 100 mK, further comprising a PdAu resistive layer, configured as a set of resistive elements to damp respective Josephson junctions
 10. The superconducting integrated circuit according to claim 1, wherein the plurality of superconducting layers comprise niobium, and the at least one intervening insulating layer comprises silicon nitride.
 11. The superconducting integrated circuit according to claim 1, wherein the current distribution network comprises a meander inductor.
 12. The superconducting integrated circuit according to claim 1, further at least one Josephson junction is diffused with deuterium.
 13. The superconducting integrated circuit according to claim 1, configured as a controller for at least one qubit operating at the cryogenic temperature.
 14. A method of forming an integrated circuit on a substrate configured to operate at a cryogenic temperature, comprising: forming and patterning a kinetic inductance layer over the substrate, patterned into a current distribution network; depositing a plurality of superconducting layers and intervening insulating layers over the kinetic inductance layer; and patterning the plurality of superconducting layers and intervening insulating layers into a plurality of Josephson junctions, the kinetic inductance layer having a higher unit inductance than the respective plurality of superconductive layers at the cryogenic temperature.
 15. The method according to claim 14, further comprising forming a resistive layer over the Josephson junctions, configured as a set of resistive elements to damp respective Josephson junctions, wherein the at least one insulating layer is planarized.
 16. The method according to claim 14, wherein the kinetic inductance layer has kinetic inductance of at least 5 pH/square and the cryogenic temperature is less than 100 mK.
 17. The method according to claim 14, wherein the plurality of superconducting layers comprise niobium, and at least one of the intervening insulating layers comprises silicon nitride.
 18. The method according to claim 14, wherein the current distribution network is patterned as a meander inductor.
 19. The method according to claim 14, further comprising interconnecting the Josephson junctions to form a controller for at least one qubit operating at the cryogenic temperature.
 20. An integrated circuit system, comprising: a substrate; a kinetic inductance layer configured as a current distribution network comprising meander inductors, formed over the substrate; a plurality of stacked superconducting layers and intervening insulating layers, patterned into a plurality of Josephson junctions, the plurality of Josephson junctions receiving current from the meander inductors of the current distribution network; and a patterned resistive layer, configured as damping elements for the plurality of Josephson junctions. 